Towards Secure Heterogeneous Integration

diagram showing three-tier security approach for secure heterogeneous integration at the chiplet, interposer, and system level.
Department of Electrical & Computer Engineering, University of Florida, Gainesville, 32611, FL, USA

University of Florida  paper proposing a three-tier security approach for secure heterogeneous integration considering supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system level. 

Florida Institute for Cybersecurity (FICS) Research, Department of Electrical & Computer Engineering, University of Florida:  The paper provides a good background on the issue of of secure heterogeneous integration and how hardware security and trust assurance have become vital aspects of design and system development.  At the chiplet level the paper outlines the issue of a lack of universal standards or independent trust validation for security assurance. It also discusses the need for new detection techniques to ensure HI packaging integrity. It is not that these security issues do not exist in more traditional electronic systems design and fabrication, it is that the new approach to systems design using HI has opened up avenues for research and
development to resolve security issues within the HI design context.

 

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